As a main memory to store commands and data, a dynamic random access memory (DRAM) with a large capacity and a low price is used. This memory has a low access speed of about tens of nanoseconds. On the other hand, a master device such as a microprocessor on the memory-access-request-issuing side has an operation speed of tens of MHz, close to 100 MHz, to hundreds of MHz. Thus, the difference between this and the DRAM access speed prevents the enhancement of performance.
To enhance the performance microprocessors are provided with a primary cache memory composed of a static memory in the chip, thereby reducing the number of accesses to DRAM. Also, in DRAM, by giving a row address, one-row of data are first read out by a sense amplifier, and then a target data is read out by giving a column address. However, when the microprocessor is provided with the primary cache memory and the DRAM access is limited to continuous address data within a certain range, the access speed can be enhanced by giving the row address only one time, then changing the column address.
After the memory access is accelerated, the next problem comes to the data transfer rate between the processor and the memory. With the primary cache to allow several data to be, in the lump, written in or read out from the memory, the flowing direction of data is fixed as long as one access is conducted. Using this, the data transfer rate can be enhanced by synchronizing the data transfer with the clock signal. A synchronous DRAM is taken as an example of that.
Further, there is DRAM that is provided with a higher clock frequency and transfer rate (hereinafter referred to as `high-speed DRAM`) by limiting the external bus to a short length and using properly the clock signal according to the transfer direction of data, i.e., reading or writing, to speed up the data transfer.
Meanwhile, Japanese patent application laid-open No. 6-266616 (1994) discloses a technique that, by providing a mechanism for detecting DRAM being read out continuously and a pre-read mechanism for reading data without waiting a request from the microprocessor when the continuous reading is detected, the apparent access time can be reduced.
In the conventional high-speed DRAM, when the master device issues an access request to the memory, the memory side judges whether it is accessible or not. It returns an acknowledge signal when accessible, and returns a non-acknowledge signal when not accessible. After receiving the acknowledge signal, the data transfer is conducted. Thus, the two-stage exchange needs to access data. Therefore, though the data transfer rate is high, it takes a long time until a first access.
To solve this problem, a concurrent high-speed DRAM was developed in which the state of memory is stored in the master device and the exchange of the acknowledge signal is disused, thereby reducing the access time. In accessing the concurrent high-speed DRAM, the master device gives a command composed of an access kind and an address to the high-speed DRAM, measuring a time accessible to the high-speed DRAM in the master device, then conducting the data transfer. Between the command and the data transfer, there exists a time period before the high-speed DRAM is allowed to access. During this time period, a bus connecting between the memory and the master device is not used.
So, an interleave mode which is used to transfer the next access command or previous access data while using this time period is provided. However, the interleave transfer cannot be used when multiple accesses do not exist, and the access time, on the contrary, becomes longer when using the interleave mode to conduct one access only. This is because the interleave transfer always provides a time period to include the command and data of another access between the command and data of one access.
On the other hand, when a data size transferable with one access is increased, the number of commands can be reduced, thereby enhancing the performance of data transfer. However, when using the interleave transfer, multiple accesses need to be stored in the memory control circuit. Therefore, if a register enabled to retain data even to a maximum-capacity access is provided, the hardware size must be increased.
Also, there is another problem that the clock frequency of interface is different from the clock frequency of the master device. This is because, though interface part of the high-speed DRAM is standardized to have a fixed frequency, the master device has a frequency defined by a required processing performance or internal circuit composition or it has another standardized interface circuit, therefore being unable to match with the fixed frequency of a certain interface.
Furthermore, an interrupt time to memory needs to be a constant period, whereas a frequency on the side of master device may be varied with a processing amount executed and may be varied because its maximum operating frequency varies due to the dispersion of transistor performance when manufactured. This is because the memory is DRAM which needs refreshing that a refresh request is generated by an interrupt, and therefore the refreshing period is determined by the DRAM side.